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pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface rev. 04 25 october 2004 product data 1. description the pcf85116-3 is an 16 kbits (2048 8-bit) ?oating gate electrically erasable programmable read only memory (eeprom). by using redundant eeprom cells it is fault tolerant to single bit errors. in most cases multi bit errors are also covered. this feature dramatically increases reliability compared to conventional eeprom memories. power consumption is low due to the full cmos technology used. the programming voltage is generated on-chip, using a voltage multiplier. as data bytes are received and transmitted via the serial i 2 c-bus, a package using eight pins is suf?cient. only one pcf85116-3 device is required to support all eight blocks of 256 8-bit each. timing of the e/w cycle is carried out internally, thus no external components are required. a write-protection input at pin 7 (wp) allows disabling of write-commands from the master by a hardware signal. when pin 7 is high, data in the eeprom are protected. the data bytes received will not be acknowledged by the pcf85116-3 and the eeprom contents are not changed. remark: the pcf85116-3 is pin and address compatible to the pcx85xxc-2 family. the pcf85116-3 covers the whole address space of 16 kbits; address inputs are no longer needed. therefore, pins 1 to 3 are not connected. the write-protection input (wp) is on pin 7. 2. features n low power cmos: u maximum operating current 1.0 ma u maximum standby current 10 m a (at 5.5 v), typical 4 m a n non-volatile storage of 16 kbits organized as eight blocks of 256 8-bit each n single supply with full operation down to 2.7 v n on-chip voltage multiplier n serial input/output i 2 c-bus (100 kbit/s standard-mode and 400 kbit/s fast-mode) n write operations: multi byte write mode up to 32 bytes n write-protection input n read operations: u sequential read u random read n internal timer for writing (no external components) n power-on reset n high reliability by using redundant eeprom cells
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 2 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. n endurance: 1000000 erase/write (e/w) cycles at t amb =22 c n 20 years non-volatile data retention time (minimum) n pin and address compatible to the pcx85xxc-2 family n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 n latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma n offered in dip and so packages 3. quick reference data 4. ordering information 4.1 ordering options table 1: quick reference data symbol parameter conditions min typ max unit v dd supply voltage 2.7 - 5.5 v i ddr supply current read f scl = 400 khz; v dd = 5.5 v - - 1.0 ma i ddw supply current e/w f scl = 400 khz; v dd = 5.5 v - - 1.0 ma i stb standby supply current v dd = 2.7 v - - 6 m a v dd = 5.5 v - - 10 m a table 2: ordering information type number package name description version pcf85116-3p/01 dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 pcf85116-3t/01 so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 table 3: ordering options type number topside mark pcf85116-3p/01 pcf85116-3 pcf85116-3t/01 85116-3
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 3 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. block diagram fig 1. block diagram. 002aaa338 test mode register input filter address comparator column decoder i 2 c-bus control logic page register eeprom array (8 256 8) shift register address pointer hv generator row dec sequencer divider oscillator 5 6 n v ss 4 7 wp 6 5 sda scl power-on-reset pcf85116-3 v dd 8
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 4 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description 7. device selection [1] the most signi?cant bit (msb) b7 is sent ?rst. fig 2. pin con?guration. 1 2 3 4 8 7 6 5 n.c. n.c. n.c. v ss sda scl wp v dd pcf85116-3 002aaa284 table 4: pin description symbol pin description n.c. 1 not connected n.c. 2 not connected n.c. 3 not connected v ss 4 negative supply voltage sda 5 serial data input/output (i 2 c-bus) scl 6 serial clock input (i 2 c-bus) wp 7 active high write-protection input v dd 8 positive supply voltage table 5: device selection code selection device code chip enable r/ w bit b7 [1] b6 b5 b4 b3 b2 b1 b0 device 1010 mem sel 2 mem sel 1 mem sel 0 r/ w
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 5 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description 8.1 i 2 c-bus protocol the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the serial bus consists of two bidirectional lines; one for data signals (sda), and one for clock signals (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been de?ned: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. 8.1.1 bus conditions the following bus conditions have been de?ned: bus not busy both data and clock lines remain high. start data transfer a change in the state of the data line, from high-to-low, while the clock is high, de?nes the start condition. stop data transfer a change in the state of the data line, from low-to-high, while the clock is high, de?nes the stop condition. data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. 8.1.2 data transfer each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is limited to 32 bytes in the e/w mode. data transfer is unlimited in the read mode. the information is transmitted in bytes and each receiver acknowledges with a ninth bit. within the i 2 c-bus speci?cations a standard-speed mode (100 khz clock rate), a fast-speed mode (400 khz clock rate) and a high-speed mode (3.2 mhz clock rate) are de?ned. the pcf85116-3 operates in only the standard and fast-speed modes. by de?nition, a device that sends a signal is called a transmitter, and the device which receives the signal is called a receiver. the device which controls the signal is called the master. the devices that are controlled by the master are called slaves. each byte is followed by one acknowledge bit. this acknowledge bit is a high level, put on the bus by the transmitter. the master generates an extra acknowledge related clock pulse. the slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte.
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 6 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. the master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master generation of the stop condition. 8.1.3 device addressing following a start condition, the bus master must output the address of the slave it is accessing. the four msbs of the slave address are the device type identi?er (see figure 3 ). for the pcf85116-3 this is ?xed to 1010. the next three signi?cant bits of the slave address ?eld (b3, b2, b1) are the block selection bits. it is used by the host to select one out of eight blocks (1 block = 256 bytes of memory). these are, in effect, the three most signi?cant bits of the word address. the last bit of the slave address (r/ w) de?nes the operation to be performed. when r/ w is set to logic 1, a read operation is selected. 8.1.4 write operations byte/word write: for a write operation, the pcf85116-3 requires a second address ?eld. this address ?eld is a word address providing access to any one of the eight blocks of memory. upon receipt of the word address, the pcf85116-3 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. word address is automatically incremented. the master can now terminate the transfer by generating a stop condition. after this stop condition, the e/w cycle starts and the bus is free for another transmission. its duration is a maximum of 10 ms. during the e/w cycle the slave receiver does not send an acknowledge bit if addressed via the i 2 c-bus. page write: the pcf85116-3 is capable of a 32-byte page write operation. it is initiated in the same manner as the byte write operation. the master can transmit up to 32 data bytes within one transmission. after receipt of each byte, the pcf85116-3 will respond with an acknowledge. the master terminates the transfer by generating a stop condition. the maximum total e/w time in this mode is 10 ms. fig 3. slave address. 002aaa287 1010b3b2b1r/w fixed software selectable
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 7 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. after the receipt of each data byte, the six high-order bits of the memory address providing access to one of the 64 pages of the memory remain unchanged. the ?ve low-order bits of the memory address will be incremented only (see figure 4 ). by these ?ve bits a single byte within the page in access is selected. by an increment the memory address may change from 31 to 0, from 63 to 32, etc. if the master transmits more than 32 bytes prior to generating the stop condition, data within the addressed page may be overwritten and unpredictable results may occur. as in the byte write operation, all inputs are disabled until completion of the internal write cycles. remark: write accesses to the eeprom are enabled if the pin wp is low. when wp is high the eeprom is write-protected and no acknowledge will be given by the pcf85116-3 when data is sent. however, an acknowledge will be given after the slave address and the word address. fig 4. auto-increment of memory address. b2 b3 b1 word address 002aaa288 read: auto increment write: unchanged write: auto increment fig 5. auto increment memory address; two byte write. s 1010 0 b1 b2 b3 a word address aa data p slave address acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave a data r/w auto increment word address auto increment word address 002aaa291
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 8 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.1.5 read operations read operations are initiated in the same manner as write operations with the exception that the lsb of the slave address (r/ w) is set to logic 1. there are three basic read operations: current address read, random read, and sequential read. remark: during read operations all bits of the memory address are incremented after each transmission of a data byte. contrary to write operations, an over?ow of the memory address occurs from 2047 to 0 (see figure 8 ). fig 6. page write operation; 32 bytes. s1010 0 b1 b2 b3 a word address a a data n acknowledge from slave acknowledge from slave acknowledge from slave r/w auto increment word address acknowledge from slave a data n + 1 auto increment word address 002aaa292 p acknowledge from slave a data n + 31 auto increment word address last byte slave address
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 9 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 7. master reads pcf85116-3 slave after setting word address (write word address; read data); sequential read. s1010 0 b1 b2 b3 a word address a a acknowledge from slave acknowledge from slave acknowledge from slave r/w acknowledge from master a data auto increment word address 002aaa293 p no acknowledge from master 1 data auto increment word address last byte r/w s1 b1 b2 b3 n bytes at this moment master transmitter becomes master receiver and eeprom slave receiver becomes slave transmitter slave address slave address 1010 fig 8. master reads pcf85116-3 immediately after ?rst byte (read mode); current address read. s 1 b1 b2 b3 a data a1 data acknowledge from slave acknowledge from master no acknowledge from master r/w auto increment word address 002aaa294 auto increment word address n bytes last bytes p slave address 1010
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 10 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. limiting values [1] esd human body model q22 at t amb =22 c; discharge procedure according to mil-std-883c method 3015. table 6: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.3 +6.5 v v i input voltage on any input pin | z i | > 500 w v ss - 0.8 +6.5 v i i input current on any input pin - 1 ma i o output current - 10 ma t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +85 c v esd electrostatic discharge voltage [1] 2-kv
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 11 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. characteristics [1] the bus capacitance ranges from 10 to 400 pf (c b = total capacitance of one bus line in pf). table 7: characteristics v dd = 2.7 to 3.5 v; v ss =0v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.7 - 5.5 v i ddr supply current read f scl = 400 khz; v dd = 5.5 v - - 1.0 ma i ddw supply current e/w f scl = 400 khz; v dd = 5.5 v - - 1.0 ma i dd(stb) standby supply current v dd = 2.7 v - - 6 m a v dd = 5.5 v - - 10 m a sda input/output (pin 5) v il low level input voltage - 0.8 - 0.3v dd v v ih high level input voltage 0.7v dd - +6.5 v v ol1 low level output voltage i ol = 3 ma; v dd(min) - - 0.4 v v ol2 i ol = 6 ma; v dd(min) - - 0.6 v i lo output leakage current v oh =v dd --1 m a t o(f) output fall time from v ihmin to v ilmax [1] with up to 3 ma sink current at v ol1 20 + 0.1c b - 250 ns with up to 6 ma sink current at v ol2 20 + 0.1c b - 250 ns t sp pulse width of spikes suppressed by ?lter 0 - 100 ns c i input capacitance v i =v ss - - 10 pf scl input (pin 6) v il low level input voltage - 0.8 - 0.3v dd v v ih high level input voltage 0.7v dd - +6.5 v i li input leakage current v i =v dd or v ss -- 1 m a f scl clock input frequency 0 - 400 khz t sp pulse width of spikes suppressed by ?lter 0 - 100 ns c i input capacitance v i =v ss --7 pf wp input (pin 7) v il low level input voltage - 0.8 - 0.1v dd v v ih high level input voltage 0.9v dd -v dd + 0.8 v data retention time t s data retention time t amb =55 c 20 - - years
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 12 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. i 2 c-bus characteristics [1] the hold time required (not greater than 300 ns) to bridge the unde?ned region of the falling edge of scl must be internally provided by a transmitter. [2] c b = total capacitance of one bus line in pf. table 8: i 2 c-bus characteristics all of the timing values are valid within the operating supply voltage and ambient temperature range and refer to v il and v ih with an input voltage swing from v ss to v dd ; see figure 9 . symbol parameter conditions standard mode fast mode unit min max min max f scl clock frequency 0 100 0 400 khz t buf time the bus must be free before new transmission can start 4.7 - 1.3 - m s t hd;sta start condition hold time after which ?rst clock pulse is generated 4.0 - 0.6 - m s t low low level clock period 4.7 - 1.3 - m s t high high level clock period 4.0 - 0.6 - m s t su;sta set-up time for start condition repeated start 4.7 - 0.6 - m s t hd;dat data hold time for cbus compatible masters 5 - - - m s for i 2 c-bus devices [1] 0- 0 -ns t su;dat data set-up time 250 - 100 - ns t r sda and scl rise time - 1000 20 + 0.1c b [2] 300 m s t f sda and scl fall time - 300 20 + 0.1c b [2] 300 ns t su;sto set-up time for stop condition 4.0 - 0.6 - m s p = stop condition; s = start condition. fig 9. timing requirements for the i 2 c-bus. mba705 t buf hd;sta t scl sda p s t low t r hd;dat t su;dat t t f t high s hd;sta t su;sta t su;sto t p
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 13 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. write cycle limits table 9: write cycle limits the power-on-reset circuit resets the i 2 c-bus logic with a set-up time of 10 m s. enabling the chip is achieved by connecting the wp input to v ss . symbol parameter conditions min typ max unit e/w cycle timing t e/w e/w cycle time - - 10 ms endurance n e/w e/w cycle per byte t amb = - 40 to +85 c 100000 - - cycles t amb =22 c 1000000 - - cycles
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 14 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. package outline fig 10. so8 (sot96-1). unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 15 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 11. dip8 (sot97-1). references outline version european projection issue date iec jedec jeita sot97-1 99-12-27 03-02-13 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.045 0.17 0.02 0.13 b 2 050g01 mo-001 sc-504-8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 16 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. soldering 14.1 introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. 14.2 through-hole mount packages 14.2.1 soldering by dipping or by solder wave typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?ed maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 14.3 surface mount packages 14.3.1 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all the bga and ssop-t packages
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 17 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3.2 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 18 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14.4 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] hot bar soldering or manual soldering is suitable for pmfp packages. [5] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [6] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [7] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [8] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [9] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 10: suitability of ic packages for wave, re?ow and dipping soldering methods mounting package [1] soldering method wave re?ow [2] dipping through-hole mount dbs, dip, hdip, rdbs, sdip, sil suitable [3] - suitable through-hole- surface mount pmfp [4] not suitable not suitable - surface mount bga, lbga, lfbga, sqfp, ssop-t [5] , tfbga, vfbga not suitable suitable - dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [6] suitable - plcc [7] , so, soj suitable suitable - lqfp, qfp, tqfp not recommended [7][8] suitable - ssop, tssop, vso, vssop not recommended [9] suitable -
philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface product data rev. 04 25 october 2004 19 of 21 9397 750 14217 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15. revision history table 11: revision history rev date cpcn description 04 20041025 - product data (9397 750 14217) modi?cations: ? table 2 ordering information on page 2 : C adjusted type number to include /01 C remove north america column ? added table 3 ordering options on page 2 (topside mark) ? section 8.1.2 data transfer on page 5 : third paragraph re-written. 03 20020819 - product data (9397 750 10249); engineering change notice 853-2356 28772; supersedes data in data sheet pcf85116-3_2 dated 1997 apr 02 (9397 750 01994).
9397 750 14217 philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 25 october 2004 20 of 21 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 19. licenses level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 25 october 2004 document order number: 9397 750 14217 contents philips semiconductors pcf85116-3 2048 8-bit cmos eeprom with i 2 c-bus interface 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 device selection. . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1.1 bus conditions . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1.2 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1.3 device addressing . . . . . . . . . . . . . . . . . . . . . . 6 8.1.4 write operations . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.5 read operations . . . . . . . . . . . . . . . . . . . . . . . . 8 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 i 2 c-bus characteristics . . . . . . . . . . . . . . . . . . 12 12 write cycle limits . . . . . . . . . . . . . . . . . . . . . . . 13 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14.2 through-hole mount packages . . . . . . . . . . . . 16 14.2.1 soldering by dipping or by solder wave . . . . . 16 14.2.2 manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 14.3 surface mount packages . . . . . . . . . . . . . . . . 16 14.3.1 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 14.3.2 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 14.3.3 manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 14.4 package related soldering information . . . . . . 18 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 16 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 17 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 19 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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